1. Field of the Invention
The present invention relates generally to integrated circuits, and more particularly to integrated circuit fabrication processes and structures.
2. Description of the Background Art
P-channel metal oxide semiconductor (PMOS) field effect transistors (FETs) fabricated using dual doped gate technology and with nitrided gate oxide (NGOX) layers have been found to exhibit negative bias temperature instability (NBTI) after voltage and temperature stressing. This instability gives rise to problems that under negative gate bias voltage, the magnitude of threshold voltage (Vt) of the FET increases and drain saturation current (IDSat) decreases. This mechanism is known to cause degradation of performance of the PMOS FETs and, in particular, loss of speed over time. In contrast FETs fabricated using single doped gate technology and with pure silicon dioxide (SiO2) gate oxides typically do not exhibit NBTI problems.